1. Field of the Invention
The present invention relates to a nonvolatile memory device, in particularly to a magnetic random access memory (MRAM) device on which a data read operation is performed referring to a reference cell.
2. Description of a Related Art
In some cases, operation for reading data stored in a memory cell of a semiconductor memory device such as MRAM (Magnetic Random Access Memory) and FRAM (Ferroelectric Random Access Memory) is performed referring to a reference cell. For example, in the case of MRAM, the amount of current read from a memory cell and the amount of current read from a reference cell are compared to one another to identify data stored in the memory cell. Furthermore, in the case of FRAM, a voltage appearing on a reference bit line when a reference cell is connected to the reference bit line and a voltage appearing on a bit line when a memory cell is connected to the bit line are compared to one another to identify data stored in the memory cell.
FIG. 11 illustrates a memory cell array 101 of a MRAM of a related art. The memory cell array 101 includes word lines W1 to Wm (m: natural number, m greater than 1) and bit lines B1 to Bn. (n: natural number, n greater than 1) At individual positions at which the word lines W1 to Wm and the bit lines B1 to Bn intersect one another are disposed memory cells. The memory cell disposed at the position at which, the word line Wi and the bit line Bj intersect one another is denoted by a memory cell xe2x80x9cCij.xe2x80x9d
FIG. 12 illustrates the structure of the memory cell Cij. The memory cell Cij includes a fixed layer 111, a data storage layer 112 and a tunnel insulation film 113. The fixed layer 111 is connected to the word line Wi and the data storage layer 112 is connected to the bit line Bj. Both the fixed layer 111 and the data storage layer 112 consist of a ferromagnetic material and respectively have a spontaneous magnetization. The tunnel insulation film 113 is disposed between the fixed layer 111 and the data storage layer 112, and formed to have a film thickness for allowing tunnel current to flow between the fixed layer 111 and the data storage layer 112. The film thickness of the tunnel insulation film 113 is typically 1.5 nm.
As shown in FIG. 13, the memory cell Cij stores data xe2x80x9c0xe2x80x9d or data xe2x80x9c1xe2x80x9d therein depending on directions of spontaneous magnetizations of the fixed layer 111 and the data storage layer 112. The direction of the spontaneous magnetization of the fixed layer 111 is being fixed. The direction of the spontaneous magnetization of the data storage layer 112 can freely be inverted and coincides with one of two directions, i.e., the same direction as that of the spontaneous magnetization of the fixed layer 111 and the direction reverse to that of the spontaneous magnetization thereof. When the directions of spontaneous magnetizations of the fixed layer 111 and the data storage layer 112 coincide with each other, the spontaneous magnetizations of the fixed layer 111 and the data storage layer 112 are denoted as xe2x80x9cparallelxe2x80x9d and when the directions of spontaneous magnetizations of the fixed layer 111 and the data storage layer 112 are opposite each other, the spontaneous magnetizations of the fixed layer 111 and the data storage layer 112 are denoted as xe2x80x9canti-parallel.xe2x80x9d The memory cell Cij has one of xe2x80x9cparallelxe2x80x9d state indicating the directions of spontaneous magnetizations of the fixed layer 111 and the data storage layer 112 are parallel to each other and xe2x80x9canti-parallelxe2x80x9d state indicating the directions thereof are opposite each other, and an electrical state corresponding to the xe2x80x9cparallelxe2x80x9d state indicating the directions of spontaneous magnetizations of the fixed layer 111 and the data storage layer 112 are parallel to each other is made to correspond to one of data xe2x80x9c0xe2x80x9d and data xe2x80x9c1,xe2x80x9d and an electrical state corresponding to the xe2x80x9canti-parallelxe2x80x9d state indicating the directions thereof are opposite each other is made to correspond to the other of data xe2x80x9c0xe2x80x9d and data xe2x80x9c1.xe2x80x9d Hereinafter, explanation will be made assuming that an electrical state corresponding to the xe2x80x9cparallelxe2x80x9d state indicating the directions of spontaneous magnetizations of the fixed layer 111 and the data storage layer 112 are parallel to each other corresponds to data xe2x80x9c1,xe2x80x9d and an electrical state corresponding to the xe2x80x9canti-parallelxe2x80x9d state indicating the directions thereof are opposite each other corresponds to data xe2x80x9c0.xe2x80x9d
Data stored in the memory cell Cij is identified utilizing a change of resistance value of the tunnel insulation film 113 due to tunnel magneto-resistance effect (TMR effect). The resistance of the tunnel insulation film 113 varies depending on the states, i.e., the xe2x80x9cparallelxe2x80x9d state indicating the directions of spontaneous magnetizations of the fixed layer 111 and the data storage layer 112 are parallel to each other, and the xe2x80x9canti-parallelxe2x80x9d state indicating the directions thereof are opposite each other. That is, the first resistance of the tunnel insulation film 113 when the spontaneous magnetizations of the fixed layer 111 and the data storage layer 112 are in the xe2x80x9canti-parallelxe2x80x9d state is larger than the second resistance thereof when the spontaneous magnetizations of the fixed layer 111 and the data storage layer 112 are in the xe2x80x9cparallelxe2x80x9d state by 10 to 40% of the second resistance. Thus, data stored in the memory cell Cij is identified utilizing a difference in resistance of the tunnel insulation film 113.
Data stored in the memory cell Cij is read based on current flowing between the word line Wi and the bit line Bj. When the data stored in the memory cell Cij is read, a specific potential difference is applied between the word line Wi and the bit line Bj. The amount of current flowing between the word line Wi and the bit line Bj by applying the specific potential difference therebetween varies depending on the resistance of the tunnel insulation film 113. Since the resistance of the tunnel insulation film 113 varies depending on the states corresponding to the directions of spontaneous magnetizations of the fixed layer 111 and the data storage layer 112, the data stored in the memory cell Cij can be identified based on current flowing between the word line Wi and the bit line Bj.
In this case, the data stored in the memory cell Cij can be identified referring to a reference cell that has a structure similar to that of a memory cell. As shown in FIG. 11, the memory cell array 101 has reference cells R1 to Rm provided therein, each of which includes previously determined data written thereinto. The reference cells R1 to Rm all are connected to a reference bit line Br. The reference cells R1 to Rm are connected respectively to word lines W1 to Wm. Data stored in memory cells Ci1 to Cin, which are connected to the word line Wi, is read referring to the reference cell Ri.
The reference cells R1 to Rm are designed so that current I(Ref) flowing through each of the reference cells R1 to Rm satisfies the following equation.
I(1) greater than I(Ref) greater than I(0)xe2x80x83xe2x80x83(1)
I(0): current flowing through a memory cell storing data xe2x80x9c0xe2x80x9d
I(1): current flowing through a memory cell storing data xe2x80x9c1xe2x80x9d
The data stored in the memory cell Cij is identified by comparing current flowing through the memory cell Cij and the current flowing through the reference cell Ri with each other. When the memory cell Cij is identified, a specific potential difference is applied between the word line Wi and the reference bit line Br to pass current through the reference cell Ri. Furthermore, a specific voltage is applied between the word line Wi and the bit line Bj to pass current through the memory cell Cij. Furthermore, a specific potential difference is applied between the word line Wi and the bit line Bj to pass current through the memory cell Cij. The amount of current having flowed through the memory cell Cij and the amount of current having flowed through the reference cell Ri are compared with each other, and when the amount of current having flowed through the memory cell Cij is larger than that of current having flowed through the reference cell Ri, the data stored in the memory cell Cij. is identified as xe2x80x9c1,xe2x80x9d and when the amount of current having flowed through the memory cell Cij is smaller than that of current having flowed through the reference cell Ri, the data stored in the memory cell Cij is identified as xe2x80x9c0.xe2x80x9d
In the semiconductor memory device constructed as described above, a memory cell exhibiting variation in its electrical performance adversely affects operation for stably identifying data stored in a memory cell. When a memory cell exhibits larger variation in its electrical performance, a differential amount between currents flowing respectively through a memory cell and a reference cell, which amount can be used to identify data stored in a memory cell, becomes smaller. In order to address problems caused by such unfavorable decrease in the differential amount, a designer has to design circuits associated with a reference cell and an identification of data with high accuracy or to design the circuits associated therewith at the expense of access speed at which a reading operation is performed.
An object of the present invention is to provide a magnetic memory device capable of suppressing influence of variation in electrical performance of memory cell and stably identifying data stored in the memory cell.
Another object of the present invention is to provide a magnetic memory device having a capability to suppress influence of variation in electrical performance of memory cell and stably identify data stored in a memory cell, and further occupying a small area.
A magnetic memory device as claimed in the present invention includes a reference cell, a first memory cell, a second memory cell located nearer the first memory cell than the reference cell and a data read circuit provided therein. The data read circuit identifies first data stored in the first memory cell based on a reference cell electrical state of the reference cell and a first electrical state of the first memory cell. Furthermore, the data read circuit identifies second data stored in the second memory cell based on the first electrical state of the first memory cell and a second electrical state of the second memory cell.
In the magnetic memory device, the second data stored in the second memory cell is identified by referring to the first memory cell located nearer the second memory cell than the reference cell, whereby a degree to which variation in electrical performance of memory cell affects stability to identify data is suppressed. In general, regarding two memory cells, variation in electrical performance of memory cell due to the process variation in the manufacture of semiconductor memory device becomes smaller when a distance between the two memory cells becomes shorter. Accordingly, in many cases, a degree to which electrical performances of the second memory cell and the first memory cell differs from each other is smaller than that to which electrical performances of the second memory cell and the reference cell differs from each other. In the magnetic memory device, the second data stored in the second memory cell is identified by referring to the first memory cell because it is believed that in many cases, a degree to which electrical performance of the first memory cell differs from that of the second memory cell is smaller than a degree to which electrical performance of the reference cell differs from that of the second memory cell. Accordingly, this operation makes stability to identify data stored in an associated memory cell enhanced.
The data read circuit preferably includes a first comparator for outputting a first comparison result signal indicating whether reference cell storage data stored in the reference cell and the first data stored in the first memory cell coincide with each other or are different from each other based on the reference cell electrical state and the first electrical state, a first data reproduction circuit for reproducing the first data based on the reference cell storage data and the first comparison result signal, a second comparator for outputting a second comparison result signal indicating whether the first data and the second data coincide with each other or are different from each other based on the first electrical state and the second electrical state, and a second data reproduction circuit for reproducing the second data stored in the second memory cell based on the first data and the second comparison result signal.
The above-described semiconductor memory device becomes particularly preferable when the semiconductor memory device is constructed such that each of the reference cell, the first memory cell and the second memory cell includes a tunnel magneto-resistance effect element comprising a first ferromagnetic thin film layer, a second ferromagnetic thin film layer and a tunnel insulation film interposed between the first ferromagnetic thin film layer and the second ferromagnetic thin film layer. The reference cell and the memory cell each consisting of a tunnel magneto-resistance effect element are apt to exhibit variation due to the process variation in the manufacture of semiconductor memory device. The semiconductor memory device constructed as described above exhibits its effectiveness to the fullest extent when the configuration thereof is applied to a semiconductor memory device comprising a reference cell and a memory cell each consisting of a tunnel magneto-resistance effect element.
In addition, above-described semiconductor memory device becomes particularly preferable when the semiconductor memory device is constructed such that each of the reference cell, the first memory cell and the second memory cell includes a MOS transistor having a floating gate therein. The reference cell and the memory cell each consisting of a MOS transistor having a floating gate therein are apt to exhibit variation due to the process variation in the manufacture of semiconductor memory device. The semiconductor memory device constructed as described above exhibits its effectiveness to the fullest extent when the configuration thereof is applied to a semiconductor memory device comprising the reference cell, the first memory cell and the second memory cell each consisting of a MOS transistor having a floating gate therein.
Preferably, the above-described semiconductor memory device further comprises one signal line, in which each of the reference cell, the first memory cell and the second memory cell is enabled by the one signal line.
The above-described semiconductor memory device may comprise a third memory cell and a fourth memory cell located nearer the third memory cell than the reference cell. In this case, preferably, the data read circuit identifies third data stored in the third memory cell based on the reference cell electrical state and a third electrical state of the third memory cell, and further, identifies fourth data stored in the fourth memory cell based on the third electrical state and a fourth electrical state of the fourth memory cell. In the semiconductor memory device constructed as described above, both the first data stored in the first memory cell and the third data stored in the third memory cell are identified by referring to the one reference cell, meaning that plural memory cells share the one reference cell to be referred when a read operation is performed on the plural memory cells. Since the reference cell to be referred is shared by plural memory cells, the semiconductor memory device configured to have such a reference cell provided therein is able to reduce its area.
In this case, the semiconductor memory device further comprises a first signal line, a second signal line and a third signal line, in which preferably, the reference cell is enabled by the first signal line, the first memory cell and the second memory cell are enabled by the second signal line, and the third memory cell and the fourth memory cell are enabled by the third signal line.
The semiconductor memory device as claimed in the present invention comprises a memory cell array having there in a plurality of memory cells disposed in a matrix, a reference cell column having therein a plurality of reference cells disposed in a column and a data read circuit. The data read circuit is provided for identifying first data stored in a first memory cell included in the plurality of memory cells and located on an outermost periphery of the memory cell array based on a reference cell electrical state of a nearest reference cell included in the plurality of reference cells and located nearest the first memory cell, and a first electrical state of the first memory cell, and further identifying second data stored in a second memory cell included in the plurality of memory cells and located adjacent to the first memory cell based on the first electrical state and a second electrical state of the second memory cell. In the above-described semiconductor memory device, a read operation is performed on the second memory cell by referring to the first memory cell because it is believed that in many cases, a degree to which electrical performance of the first memory cell differs from that of the second memory cell is smaller than a degree to which electrical performance of the reference cell differs from that of the second memory cell. Accordingly, stability to identify data stored in the second memory cell is enhanced. Moreover, a distance between the first memory cell and the reference cell is minimized, enhancing stability to identify data stored in the first memory cell.
Preferably, the nearest reference cell, the first memory cell and the second memory cell are enabled by the one signal line.
The semiconductor memory device as claimed in the present invention comprises a memory cell array having there in a plurality of memory cells disposed in a matrix, a reference cell and a data read circuit. The data read circuit is provided for identifying first data stored in a first memory cell included in the plurality of memory cells and located on an outermost periphery of the memory cell array based on a reference cell electrical state of the reference cell and first electrical state of the first memory cell, and identifying second data stored in a second memory cell included in the plurality of memory cells and located adjacent to the first memory cell based on the first electrical state and a second electrical state of the second memory cell, and then, identifying third data stored in a third memory cell included in the plurality of memory cells and located on an outermost periphery of the memory cell array, the third memory cell being different from the first memory cell, based on the reference cell electrical state and a third electrical state of the third memory cell, and further, identifying fourth data stored in fourth memory cell included in the plurality of memory cells and located adjacent to the third memory cell based on the third electrical state and a fourth electrical state of the fourth memory cell.
A method of reading data from a semiconductor memory device as claimed in the present invention comprises: identifying first data stored in a first memory cell based on a reference cell electrical state of a reference cell and a first electrical state of the first memory cell; and identifying second data stored in a second memory cell located nearer the first memory cell than the reference cell based on the first electrical state and a second electrical state of the second memory cell.
In this case, preferably, the step includes: producing a first comparison result signal indicating whether reference cell storage data stored in the reference cell and the first data stored in the first memory cell coincide with each other or are different from each other based on the reference cell electrical state and the first electrical state; and reproducing the first data based on the reference cell storage data and the first comparison result signal, and the step includes: outputting a second comparison result signal indicating whether the first data stored in the first memory cell and the second data stored in the second memory cell coincide with each other or are different from each other based on the first electrical state and the second electrical state; and reproducing the second data based on the first data and the second comparison result signal.
A method of reading data from a semiconductor memory device as claimed in the present invention is applied to a semiconductor memory device comprising a plurality of row lines extending in a first direction, a plurality of column lines extending in a direction different from the first direction, a plurality of memory cells each being provided at intersections at which the plurality of row lines and the plurality of column lines intersect one another and each being comprised of two ferromagnetic thin film layers interposing an insulation film therebetween, a reference column line provided adjacent to an outermost column line out of the plurality of column lines and intersecting the plurality of row lines, and a plurality of reference elements each being provided at intersections at which the reference column line and the plurality of row lines intersect one another. The method of reading data from the semiconductor memory device constructed as described above comprises: optionally selecting one row line out of the plurality of row lines; comparing the reference element in the one row line being selected and a first memory cell in the one row line being selected with each other; and comparing the first memory cell in the one row line being selected and a second memory cell in the one row line being selected with each other.
A method of reading data from a semiconductor memory device as claimed in the present invention is applied to a semiconductor memory device comprising: at least one row line; first and second column lines respectively intersecting the at least one row line; first and second non-volatile memory cells each being provided at intersections at which the at least one row line and the first and second column lines intersect one another; at least one reference column line intersecting the at least one row line; and at least one reference cell provided in the at least reference column line. The method comprises: selecting a first memory cell and the reference cell; identifying data written into the first memory cell by comparing a current flowing through the first column line based on data written into the first memory cell and a current flowing through the at least one reference column line based on data stored in the reference cell with each other; selecting the first memory cell and the second memory cell; comparing a current flowing through the second column line based on data written into the second memory cell and a current flowing through the first row line based on data written into the first memory cell with each other; and identifying data written into the second memory cell based on a comparison result obtained by comparing said two currents used to identify data written into the second memory cell and a result obtained by identifying data written into the first memory cell.
Particularly, the method of reading data from a semiconductor memory device is preferably employed to perform a read operation on a semiconductor memory device in which each of the first and second memory cells and the reference cell includes two ferromagnetic thin film layers interposing an insulation film therebetween.
Furthermore, in order to more securely identify data stored in a memory cell, preferably, the reference cell is disposed adjacent to the first memory cell and the first memory cell is disposed adjacent to the second memory cell.